The MPEG-4 encoder is a hardware module optimized for FPGA technologies, making use of a limited number of logic resources and being able to encode a 4CIF (704x576) sequence in real time.
It is fully compliant with the Video part of ISO/IEC 14496-2. All visual tools of the Simple Profile are implemented, including full support of I-VOP (intra-coded frames, without motion estimation) and P-VOP (predictive-coded frame, with motion estimation on previously encoded frame). The core is a good compromise between coding efficiency (resulting in lower bit rate for same quality), logic complexity and coding throughput, thanks to the use of an efficient motion estimation algorithm (directional search) leading to fast and precise matching, at half pixel resolution, of blocks between the current frame and its reference.
Supported image resolutions include pre-defined levels Level1 to Level5(QCIF/CIF/VGA/SDTV) and custom definitions up to 4CIF (704x576). The core can be customized to provide support for even larger resolutions, such as HD format.
The core features a Variable Bit Rate mode (VBR mode: fixed, user-specified quality). It can optionally also provide Constant Bit Rates (CBR mode: with regulation of the output bit rate) by using an external small microprocessor running a rate allocation algorithm (such as Nios or Microblaze). When used in CBR mode, the core delivers high-quality regulation thanks to its patented rate allocation algorithm making use of statistical information available at the motion estimation engine.
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