IP cores
Memory control
Barco Silex offers a broad portfolio of high-quality, silicon-proven "memory controllers" for system-on-chip designs. As a leading provider of connectivity IP, Barco Silex delivers the industry's most comprehensive solution for widely used protocols such as USB, PCI Express, and DDR. Combined with a robust IP development and verification methodology, extensive investment in quality and comprehensive technical support, Barco Silex IP enables designers to accelerate time-to-market and reduce integration risk.
Our controllers are built upon a tradition of high performance and highly customizable memory subsystem design. The many generic optional features available in our IP cores allow the customer to get the best possible trade-off between performance and area and to meet each and every customer's application requirements.
The DDR controllers are licensed in Verilog or VHDL RTL code format. They are synthesizable to virtually any ASIC and FPGA technology and supports the standard PHY interface for easy system integration. Optional features include different user interfaces such as AXI, AHB and generic user interface. Our cores are available as a single port SDRAM controller or a multi-port SDRAM controller with different bus interfaces at different bus clock speed sharing the same memory.
Most advanced standards like "ONFI" (Open NAND Flash Interface Specification) for NAND Flash device interfaces or "DFI" (DDR PHY Interface) for DDR device interfaces are supported to offer more flexibility and to make the integration work easier.
